This invention is related generally to solid state integrated circuit fabrication and more particularly, to methods for fabricating voltage programmable link structures.
Programmable conductive paths, particularly "links" between two or more distinct conductive layers, are increasingly employed in solid-state integrated circuit fabrication to produce a wide variety of programmable circuits including, for example, field programmable gate arrays ("FPGAs"), programmable read only memories ("PROMs"), and other programmable electronic devices. Typically, these devices are "programmed" by applying an electrical voltage to trigger an "antifuse" link structure between two conductive layers that are separated by an insulator to establish an electrical connection therebetween.
While this approach permits an almost limitless variety of custom circuits, certain factors make programmable devices difficult to implement. To be useful, the link structures must remain insulating at the normal operating voltage for solid state devices (e.g., nominally five volts), but must reliably "break down," or respond, to a programming voltage which is higher than the normal operating voltage. Typically, the programming voltage should be no more than about fifteen volts so that other structures on the circuit are not damaged.
If a link structure breaks down at a voltage below the programming voltage (or breakdown voltage), an unintended altered circuit will result, thereby disturbing the normal operation of the existing circuit. On the other hand, if the programmable link structure is over-resistant to the programming voltage, either the conductive path will not be formed when desired, or greater voltages must be applied with the attendant risk of damage to nearby structures on the wafer.
One way to implement a voltage programmable link structure is to use two levels of metallization agents and a composite insulator made of a deposited silicon oxide film interposed between two like films of silicon nitride. The insulator stack is deposited over the first metal and then a thin film of aluminum (in the order of 20 nm) is deposited over the insulator to protect it from etchants in a subsequent step. Next, the thin film of aluminum is patterned by etching to form patches which define potential links, and then a dielectric is deposited thereover. A portion of the dielectric is then removed over the patches, and the remainder of second metal element is deposited in the removed portion.
One problem with this approach is that the thin aluminum film deposited over the insulator has to be patterned by etching in order to keep individual links isolated. This etching process is a rather delicate matter. For example, a dry or wet etch must be strictly controlled or else the thin insulator stack will be damaged, causing a possible short between the first and second metals.
Another problem is that misalignment of the aluminum layer patches and the second metal element can result in etching of the transformable insulation layer and a short between the two metal layers. To prevent the misalignment and accompanying short from occurring, the patch must be made considerably larger than the link area. However, since the size of the patch and parasitic capacitance are linearly related, a larger patch would be accompanied by a large parasitic capacitance. Parasitic capacitance is a problem because it slows the speed of the integrated circuit and prevents it from operating efficiently.
Furthermore, it is important that the voltage programmable link structure be able to meet the expected requirements for the next generation of FPGAs (e.g., 0.8 .mu.m). It is expected that the alignment tolerance for the next generation of FPGAs will be about 0.2 .mu.m, so an actual 0.8.times.0.8 .mu.m.sup.2 link structure would require an increase in area equal to about 1.2.times.1.2 .mu.m.sup.2. The increase in size results in an increase in parasitic capacitance. Thus, there is also a need for a voltage programmable link structure that can meet the expected requirements for the next generation of FPGAs without having an increase in parasitic capacitance.